1. Field of the Invention
This invention relates generally to a window/presum operation architecture for a digital signal processor, and more particularly, to a window/presum operation architecture for a digital signal processor incorporating an efficient use of ASIC and memory chips.
2. Discussion of the Related Art
In certain processor applications, it is necessary to convert time domain data signals to frequency domain data signals. To perform such a transformation, Fast Fourier Transform (FFT) processors are most commonly used. Often, as is well known, the FFT processor performance can be enhanced by performing certain operations prior to the FFT itself. Two such operations, which are generally referred to as windowing and presumming, are very common. The windowing operation refers to a multiplication process which tailors a data block in an appropriate manner to be processed by the FFT. The presumming operation refers to an accumulation process which has the effect of reducing the size of the required FFT.
The prior art window and presum operation architectures have been implemented on high density application specific integrated circuits (ASICs) and separate memory chips. An ASIC enables a plurality of specialized functions to be performed on a single chip, as is well known in the art. Despite their success, these conventional window/presum architectures suffer from a number of drawbacks making them inefficient. Specifically, the conventional window/presum architectures require the existence of many blocks of memory imbedded within or between adjacent processing elements: this makes the number of chips required higher than need be (explained below), thus decreasing the reliability and increasing the size, weight, power and cost of the processor. In the conventional architectures, many banks of memory have been either implemented internally on the individual ASICs or externally in separate memory chips. These blocks of memory are required in the window/presum operations in order to delay data or delay window coefficients.
A number of problems arise if memory banks are included on the individual ASICs. First, the required depth of each memory block in the conventional architecture is application dependent. Consequently, the on-chip implementation lacks flexibility in that once the ASIC is built, the memory size and configuration is fixed and thus requires a new ASIC to achieve different memory capabilities for different applications. Secondly, ASICs cannot implement random access memory (RAM) very efficiently. Therefore, the on-chip method squanders ASIC resources on functions that would be better handled on specialized memory chips.
It is therefore known to remove the memory banks from the individual ASICs, and incorporate the memory on specialized memory chips. Typically, however, RAM chip Input/Output (I/O) limitations will preclude the consolidation of several of the separate RAM banks into a single memory chip. As a result, in many applications only a fraction of the storage capacity of each RAM chip will be utilized. This is a great reduction in the efficiency of the system in that a high memory chip count is required even though very dense memory chips are available in today's technology. In addition to an inefficient RAM utilization, conventional off-chip architectures also result in inefficient ASIC utilization. Although, very high capacity ASICs are available in today's market, with the off-chip memory method, ASIC I/O requirements become the limiting factor in determining how much of the window/presum architecture can be implemented in a single ASIC because each of the external RAM chips requires its own I/O ports to and from the ASIC. Consequently, conventional window/presum architectures cannot capitalize on the very high density ASIC and RAM chips which are currently available.
What is needed then is a window/presum operation architecture incorporating a reduced number of memory chips and ASICs such that the size, weight, power and cost of the processor is reduced, and the integrity and reliability of the system is increased. It is therefore an object of the present invention to provide such an architecture.